1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the control of serial scan chains used for test operations within integrated circuits.
2. Description of the Prior Art
As integrated circuits become increasingly complex, there is an increase in need the for effective test mechanisms which can be used to debug the design or programming of those integrated circuits as well as to check that they have been correctly manufactured. Serial scan chain techniques in accordance with the known IEEE 1149.1 JTAG Standard and the IEEE 1500 Standard for Embedded Core Test provide effective and well understood mechanisms for performing test operations. There exists a considerable infrastructure of tools and knowledge for using these techniques to perform test operations upon integrated circuits. Accordingly, it is advantageous to keep using these techniques where possible so that the existing capital associated therewith can be reused.
As part of the increasing complexity of integrated circuits, it is becoming common that manufacturing failures occur within part of an integrated circuit, but that that integrated circuit still has value and is useable if the other parts of that integrated circuit still function correctly. As an example, in a memory integrated circuit, it may be that one or more of the banks of memory are defective, such as due to a manufacturing defect, but that the integrated circuit as a whole will still have other functioning memory banks and can be usefully used as a lower memory capacity integrated circuit.
Another example of the increasing complexity of integrated circuits is that different circuit blocks therein may be selectively powered-down and powered-up during normal operation in order to reduce the average power consumption of the integrated circuit. It is desirable to be able to perform test operations on an integrated circuit when parts of that integrated circuit are powered-down in order to properly understand the behaviour of the integrated circuit and identify any design or manufacturing problems therein.
The paper “Scan Chain Design For Test Time Reduction in Core-Based Ics” by Joep Aerts and Erik Jan Marinissen published in proceedings of the 1998 IEEE International Test Conference pages 448-457 discloses various scan chain architectures with a view to reducing test time. One of these architectures is a daisychain architecture in which a local bypass is provided for each of a plurality of cores within an integrated circuit. Control signals are routed to multiplexers associated with each local bypass proximal to the core concerned. This arrangement suffers from the problem that a defect with a core or scan chain has an increased likelihood of also effecting the multiplexer and bypass path rendering bypassing of the defect impossible. Furthermore, as areas within an integrated circuit are selectively powered down it is a disadvantageous complexity to maintain power to a local bypass and multiplexer.